I talked the other day about the DSM2150F5 which is a DSP System Memory (DSM) which contains Flash, Digital I/O, and a PLD and was designed with the Analog Devices Blackfin DSP in mind. Now today Stretch has announced their S5000 family of processors.
The chip combines an existing RISC (reduced instruction set computing) architecture with a large reconfigurable area of programmable logic called the Instruction Set Extension Fabric, ISEF. The company's own C/C++ compiler automatically spots areas in a program that require intensive computation and creates new instructions for the processor to handle those tasks. [CNET News.com]
An interesting development and I wish them luck, but from my experience they won't make much headway. Their technology requires a close interaction between the compiler and the silicon to achieve their touted performance, which means that a port of gcc to their silicon won't do you any good. Also, if you are working on a design up front you have a good idea of where the performance bottlenecks are going to be. If you have such a performace bottleneck than you can offload just that part of the design into an FPGA or PLD and keep the rest of the processing in a more flexible DSP or CPU. The Stretch device seems to be aimed at a sector of users that are doing embedded designs but don't know where their performance bottlenecks are going to be. That, in a darwinian sense, should be a small or non-existent market. We'll call this 'aiming for the dodo'.
In general these events all point to the constant tension between picking the right mix of ASIC, FPGA and DSP to include in an embedded solution. All of those technologies have different costs, flexibility, speed, time to market, and power consumption. TI has a good whitepaper that while a bit biased towards the DSP solution provides a decent comparison of the advantages between ASICs, DSPs, FPGAs, and other solutions. The original pdf was unavailable at the time I wrote this, thus the link to the google cache of the paper.